The present invention relates to a method for forming a self aligned contact (SAC) of a semiconductor device; and, more particularly, to a method for forming an SAC that improves the margin of the SAC forming process by forming voids.
Even though the integration of a semiconductor device is increased, it is very hard to safely secure overlay accuracy and the margin of a pattern forming process that uses a photoresist. Therefore, a self aligned contact (SAC) process is developed to solve this problem. The SAC process does not uses any separate mask in the patterning and performs etching using a material that is deposited already, and thereby contributes to cost reduction. Various methods are used in the SAC process, but the most frequently used one is a method that uses a nitride layer as an etching barrier layer.
FIG. 1 is a cross-sectional view showing a process for forming an SAC using a nitride layer as an etching barrier layer according to a prior art. In the drawing, gate electrodes 11 are formed on a substrate 10, and spacers are formed on the sidewalls thereof, and an etching barrier layer formed of nitride, i.e., a hard mask 12, is formed on the gate electrodes to prevent the loss of the gate electrodes in the SAC forming process. On top of this structure, an inter-layer insulation layer 14 is deposited. The reference xe2x80x98Axe2x80x99 shows the loss of the gate electrode 11 and the hard mask 12 in the process for forming a contact plug, such as storage node or bit line. In the SAC forming process, etching is performed to the impurity junction area in the lower part of the substrate 10, and in this etching process, the loss marked as xe2x80x98Axe2x80x99 is inevitable.
In other words, in the etching process, over-etching should be performed to charge the underlying layer with electricity. Here, since the conductor layer in the upper part, such as gate electrodes 11, is open and continues to be attacked, the underlying layer is short-circuited from a conductive material, such as a subsequent plug, and thereby the electric characteristics of the semiconductor device are deteriorated, and the throughput is dropped as well. Therefore, to solve the above problems from the basics, the etching condition of high selection ratio should be developed, but this can hardly be realized.
It is, therefore, an object of the present invention to provide a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask as well as simplifies the SAC forming process.
In accordance with an aspect of the present invention, there is provided a method for forming an SAC of a semiconductor device, including the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.
In this method for forming an SAC of the present invention, a tetraethyl ortho silicate (TEOS) layer is deposited between the gate electrodes to prevent the loss of gate electrodes and hard mask. Here, the losses of gate electrodes and hard mask are prevented by forming voids to increase the etching margin in the subsequent SAC forming process.